RAM Latency

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Explain, plz.

[dgrmkrp]

SDRAM access

SDRAM is notionally organized into a grid like pattern, with "rows", and "columns". The data stored in SDRAM comes in blocks, defined by the coordinates of the row and column of the specific information. SDRAM access has four main measurements (quantified in FSB clock cycles) important in defining the SDRAM latency in a given computer:

(the 't' prefixes are for 'time')

tCAS
The number of clock cycles needed to access a certain column of Data in SDRAM. CAS Latency, or simply CAS, is known as Column Address Strobe Latency, sometimes referred to as tCL.
tRCD
The number of Clock cycles needed between a Row Address Strobe (RAS) and a CAS. It is the time required between the computer defining the row and column of the given memory block and the actual read or write to that location. Stands for Row address to Column address Delay.
tRP
The number of clock cycles needed to terminate access to an open row of memory, and open access to the next row. Stands for Row precharge time.
tRAS
The minimum number of clock cycles needed to access a certain row of data in RAM between the data request and the precharge command. Known as Active to Precharge Delay.

The steps for the memory controller to access data in SDRAM:

1. Defines which row the requested data is in (RAS)
2. Gives the RAM time to access requested row (RCD)
3. Defines the column of requested data (CAS)
4. Waits for the RAM to send requested data to the CPU
5. Precharges the row to recycle it for subsequent use (RP)


this is from wikipedia, under: http://en.wikipedia.org/wiki/RAM_latency
good luck