DDR4 memory?

[AmEv]

The sad part is?


By the time I get a DDR4 stick of RAM, it'll be considered highly outdated.
Yeah. I'm a computer modder with no income whatsoever.

[msmrx57]

Yeah. I'm a computer modder with no income whatsoever.

I'm in the same boat. My newest machine is a AMD dual core.

[Konrad]

I take it back. There are other ways to get faster RAM. The problem is they basically all involve exotic cooling like liquid nitrogen.

[AmEv]

Pentium 4

[DemonDragonJ]

I am definitely excited about this new development, but as the slowest component (i.e., the greatest bottleneck to overall performance) in a modern computer is a mechanical hard drive, how great of a performance increase shall be experienced from upgrading to DDR4 memory?

On the subject of memory, there is an issue about which I have been wondering for some time: how is it that memory with a higher operating frequency also often has a higher latency? If the operating frequency represents the number of calculations that the memory can perform in a specified duration (identical to the operating frequency of a CPU), and the latency represents the number of clock cycles (calculations) between the CPU requesting specific data from the memory and the memory providing that data, would it not be more logical for a greater number of calculations per second (a higher operating frequency) to also allow for a shorter delay between the CPU requesting data and the memory providing it (a lower latency)? Could someone here please explain that to me?

Apart from that issue, the aspect of DDR4 that most intrigues me is that, according to the Wikipedia article on DDR4 SDRAM, the multi-channel architecture of previous generations of memory shall be discarded in favor of a "point to topology, where each channel in the memory controller is connected to a single module." I hope that that transition leads to much faster performance overall.

[Konrad]

The great mechanical hard drive performance bottleneck is not so much an issue with SSD drives. The new bottlenecks are Shenzhen garbage flash controller chips and, probably soon, their mobo-connected bus speeds.

How long before they decide on the most elegant solution: separate RAM banks for each processor core?

[DemonDragonJ]

How long before they decide on the most elegant solution: separate RAM banks for each processor core?

That sounds very interesting to me, but that concept unfortunately is unfamiliar to me? Could you please either explain it in greater detail, or direct me to a web site that could provide me with further information on the subject?

[Konrad]

It seems like a simple idea to me: design the architecture so the mobo is populated with multiple RAM banks and controllers, each dedicated directly to a single processor core (or single group of cores). This would obviously be a considerable paradigm shift, requiring a new generation of processors and matched (Northbridge/MCH) chipset components; ie, wait until Intel or AMD introduces it before Gigabyte and Asus start engineering it onto PC mobos.

It seems obvious that multiple memory controllers can collectively do a better job of running multiple simultaneous memory tasks than a single controller could. As it stands, all 8 of your cores still have to share access to all external memory ... on-die L2/L3 cache is great, and fast, but surely more multiple-simultaneous bandwidth to external cache/memory can only be better? I think that conditions where one or more processor cores has to idle clock priority while waiting for other core(s) to finish their memory access is the sort of thing which happens kinda rarely but with enough statistical frequency to have noticeable impact on overall performance thresholds. Think of it as separate "channels" if you prefer, except slaved directly to the processor cores instead of to the chipset bridge, one step closer to true parallel computing (in the context of simultaneously running multiple computers on one mobo). More hardware always means more capabilities, and if it's all engineered intelligently then it can vastly exceed the sum of its parts.

It might even increase fault tolerance; allowing a locked processor or bad RAM chip to only BSoD/crash/reboot an isolated segment of the machinery while retaining the functions and data carried by the remainder.

The idea was mine, although no doubt every competent silicon engineer on the planet has already considered or studied it, no doubt there's already technical (and even corporate) terms describing such architecture, and perhaps even some (non-PC) multi-core platforms which already implement it.

PCs are great and all, don't get me wrong, I'm a nerd with passion. But as far as real computers go, consumer-class PCs are just overpriced cheap mass-produced junk, no matter how many fancy nVidia cards you stuff into them. They're compatible with common software and hardware, and with each other, and comparatively inexpensive and (these days) fairly idiot-proofed and easy to operate. Please don't flame me, lol.

[DemonDragonJ]

It seems like a simple idea to me: design the architecture so the mobo is populated with multiple RAM banks and controllers, each dedicated directly to a single processor core (or single group of cores). This would obviously be a considerable paradigm shift, requiring a new generation of processors and matched (Northbridge/MCH) chipset components; ie, wait until Intel or AMD introduces it before Gigabyte and Asus start engineering it onto PC mobos.

It seems obvious that multiple memory controllers can collectively do a better job of running multiple simultaneous memory tasks than a single controller could. As it stands, all 8 of your cores still have to share access to all external memory ... on-die L2/L3 cache is great, and fast, but surely more multiple-simultaneous bandwidth to external cache/memory can only be better? I think that conditions where one or more processor cores has to idle clock priority while waiting for other core(s) to finish their memory access is the sort of thing which happens kinda rarely but with enough statistical frequency to have noticeable impact on overall performance thresholds. Think of it as separate "channels" if you prefer, except slaved directly to the processor cores instead of to the chipset bridge, one step closer to true parallel computing (in the context of simultaneously running multiple computers on one mobo). More hardware always means more capabilities, and if it's all engineered intelligently then it can vastly exceed the sum of its parts.

It might even increase fault tolerance; allowing a locked processor or bad RAM chip to only BSoD/crash/reboot an isolated segment of the machinery while retaining the functions and data carried by the remainder.

The idea was mine, although no doubt every competent silicon engineer on the planet has already considered or studied it, no doubt there's already technical (and even corporate) terms describing such architecture, and perhaps even some (non-PC) multi-core platforms which already implement it.

PCs are great and all, don't get me wrong, I'm a nerd with passion. But as far as real computers go, consumer-class PCs are just overpriced cheap mass-produced junk, no matter how many fancy nVidia cards you stuff into them. They're compatible with common software and hardware, and with each other, and comparatively inexpensive and (these days) fairly idiot-proofed and easy to operate. Please don't flame me, lol.

Wow; that is definitely very interesting. I certainly would be interested to see if this new memory architecture becomes more popular, as it seems as if it could help computers to operate much faster and more efficiently.

Additionally, your comment about parallel computing is also intriguing, but if it becomes more popular, will serial communication (i.e., USB, PCI-express, SATA) remain the primary communication type for computer interfaces, as serial communication is superior to parallel communication, or will parallel communication become popular again? Or are parallel communication and parallel computing unrelated to each other?

[xr4man]

Or are parallel communication and parallel computing unrelated to each other?

you are correct to a certain extent.

the processor already runs parallel communications natively. that's where you get 16 bit, 32 bit, 64 bit, etc. in a 64 bit processor you have 64 bits of data going to the processor at one time in parallel. same thing with an ide port for a hard drive. the data is flowing in x amount of bits per clock cycle. with sata coms it just changes the parallel data into a single stream of serial bits.


but with parallel computing, you would have each core or processor doing it's own thing at the same time as another core or processor. whether their communications are in parallel or serial.

i think that's pretty much how they work now. however, that parallel processing has to go through a single memory controller chip. so that parallel data to and from the processor has to go through the controller chip "serially".

so what konrad is saying is if you give each core it's own memory controller, then that parallel data can go through IT'S OWN MEMORY CONTROLLER "PARALLELY" (i just made a new word).

does that make any more sense?